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Modèl Pa gen.: NSO4GU3AB
Transpòtasyon: Ocean,Air,Express,Land
Kalite peman: L/C,T/T,D/A
Incoterm: FOB,EXW,CIF
4GB 1600MHz 240-PIN DDR3 UDIMM
Istwa Revizyon
Revision No. |
History |
Draft Date |
Remark |
1.0 |
Initial Release |
Apr. 2022 |
|
Kòmann -nan tab enfòmasyon
Model |
Density |
Speed |
Organization |
Component Composition |
NS04GU3AB |
4GB |
1600MHz |
512Mx64bit |
DDR3 256Mx8 *16 |
Deskripsyon
Hengstar unbuffered DDR3 SDRAM DIMMS (Unbuffered Double Done Pousantaj Synchronous Doub nan-liy modil memwa) yo se pouvwa ki ba, gwo vitès operasyon memwa modil ki sèvi ak aparèy DDR3 SDRAM. NS04GU3AB se yon 512m x 64-ti jan de ran 4GB DDR3-1600 CL11 1.5V SDRAM pwodwi DIMM unbuffered, ki baze sou sèz 256m x 8-bit konpozan FBGA. SPD a pwograme pou JEDEC estanda latansi DDR3-1600 distribisyon 11-11-11 nan 1.5V. Chak DIMM 240-PIN itilize dwèt kontak lò. Se SDRAM a unbuffered DIMM gen entansyon pou itilize kòm memwa prensipal lè enstale nan sistèm tankou PC yo ak estasyon.
Karakteristik
: Pwovizyon pou Power: VDD = 1.5V (1.425V a 1.575V)
VDDQ = 1.5V (1.425V pou 1.575v)
800MHz FCK pou 1600MB/sec/PIN
8 Bank Endepandan Entèn
: Pwopozisyon Latansi CAS: 11, 10, 9, 8, 7, 6
Pwogramasyon aditif latansi: 0, Cl - 2, oswa CL - 1 revèy
8-ti jan pre-chache
: Longè burst: 8 (interleave san okenn limit, sekans ak adrès kòmanse "000" sèlman), 4 ak TCCD = 4 ki pa pèmèt san pwoblèm li oswa ekri [swa sou vole a lè l sèvi avèk A12 oswa MRS]
-Bi-direksyon diferans done strobe
(Entènèt (pwòp tèt ou) kalibrasyon; Entèn kalibrasyon pwòp tèt ou nan ZQ PIN (RZQ: 240 ohm ± 1%)
ou mouri revokasyon lè l sèvi avèk PIN ODT
Verage Peryòd rafrechi 7.8US nan pi ba pase TCase 85 ° C, 3.9US nan 85 ° C <TCase <95 ° C
Reyajiste
-Fly-pa topoloji
: PCB: Wotè 1.18 "(30mm)
rohs konfòme ak halogen-gratis
Kle paramèt distribisyon
MT/s |
tRCD(ns) |
tRP(ns) |
tRC(ns) |
CL-tRCD-tRP |
DDR3-1600 |
13.125 |
13.125 |
48.125 |
2011/11/11 |
Tab adrès
Configuration |
Refresh count |
Row address |
Device bank address |
Device configuration |
Column Address |
Module rank address |
4GB |
8K |
32K A[14:0] |
8 BA[2:0] |
2Gb (256 Meg x 8) |
1K A[9:0] |
2 S#[1:0] |
Deskripsyon PIN
Symbol |
Type |
Description |
Ax |
Input |
Address inputs: Provide the row address for ACTIVE commands, and the column |
BAx |
Input |
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or |
CKx, |
Input |
Clock: Differential clock inputs. All control, command, and address input signals are |
CKEx |
Input |
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry |
DMx |
Input |
Data mask (x8 devices only): DM is an input mask signal for write data. Input data is |
ODTx |
Input |
On-die termination: Enables (registered HIGH) and disables (registered LOW) |
Par_In |
Input |
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. |
RAS#, |
Input |
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being |
RESET# |
Input |
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and |
Sx# |
Input |
Chip select: Enables (registered LOW) and disables (registered HIGH) the command |
SAx |
Input |
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address |
SCL |
Input |
Serial |
CBx |
I/O |
Check bits: Used for system error detection and correction. |
DQx |
I/O |
Data input/output: Bidirectional data bus. |
DQSx, |
I/O |
Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; |
SDA |
I/O |
Serial |
TDQSx, |
Output |
Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD |
Err_Out# |
Output (open |
Parity error output: Parity error found on the command and address bus. |
EVENT# |
Output (open |
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical |
VDD |
Supply |
Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The |
VDDSPD |
Supply |
Temperature sensor/SPD EEPROM power supply: 3.0–3.6V. |
VREFCA |
Supply |
Reference voltage: Control, command, and address VDD/2. |
VREFDQ |
Supply |
Reference voltage: DQ, DM VDD/2. |
VSS |
Supply |
Ground. |
VTT |
Supply |
Termination voltage: Used for control, command, and address VDD/2. |
NC |
– |
No connect: These pins are not connected on the module. |
NF |
– |
No function: These pins are connected within the module, but provide no functionality. |
Nòt : Tablo deskripsyon PIN ki anba a se yon lis konplè nan tout broch posib pou tout modil DDR3. Tout broch ki nan lis pouvwa pa dwe sipòte sou modil sa a. Gade devwa PIN pou enfòmasyon espesifik nan modil sa a.
Dyagram blòk fonksyonèl
4GB, 512MX64 Modil (2Rank nan x8)
Dimansyon modil
View devan
View devan
Nòt:
1.Tout dimansyon yo nan milimèt (pous); Max/min oswa tipik (tip) kote te note.
2.Tolerans sou tout dimansyon ± 0.15mm sof si otreman espesifye.
3. Dyagram nan dimansyon se pou referans sèlman.
Pwodwi kategori : Endistriyèl Smart Modil Pwodwi pou Telefòn
Deklarasyon sou vi prive: Konfidansyalite ou trè enpòtan pou nou. Konpayi nou an pwomèt pou nou pa divilge enfòmasyon pèsonèl ou nan nenpòt ki EXPANY ak soti otorizasyon eksplisit ou.
Ranpli plis enfòmasyon pou ki ka jwenn an kontak ak ou pi vit
Deklarasyon sou vi prive: Konfidansyalite ou trè enpòtan pou nou. Konpayi nou an pwomèt pou nou pa divilge enfòmasyon pèsonèl ou nan nenpòt ki EXPANY ak soti otorizasyon eksplisit ou.